Port B. Port C. This port can be divided into two 4-bit ports under the mode control. Each 4-bit port contains a 4-bit latch and it can be used for the controls signal outputs and status signal inputs in conjunction with ports A and B. There are three basic modes of operation that can be selected by the systems software:.
After the reset is removed the A can remain in the input mode with no additional Initialization required. During the execution of the systems program any of the other modes may be selected using a single output Instruction. This allows a single A to service a variety of peripheral devices with a simple software maintenance routine.
All of the output registers, including the status flip-flops, will be reset whenever the mode is changed. For instance; Group B can be programmed in Mode 0 to monitor simple switch closing or display computational results, Group A could be programmed in Mode 1 to monitor a keyboard or tape reader on an interrupt-driven basis. The design of the A has taken into account things such as efficient PC board layout, control signal definition vs PC layout and complete functional flexibility to support almost any peripheral device with no use of the available pints.
This feature reduces software requirements in Control-based applications. When the A is programmed to operate in mode 1 or mode 2, control signals are provided that can used as interrupt request input to the CPU.
Note: All Mask flip-flops are automatically reset during mode selection and device reset. This functional configuration provides simple input operations for each of the three ports. Mode 1 Basic Functional Definitions:. STB Strobe Input. In essence, an acknowledgement. It is reset by the falling edge of RD. This procedure allows an input device to request service from the CPU by simply strobing its data into port.
ACK Acknowledge Input. Used to select port from which data is to be transmitted or to which data is to be transmitted. Port A. Port B. Port C.
Control Word Register. To indicate read operation. To indicate write operation. PA 0 -PA 7. PB 0 -PB 7. PC 0 -PC 3. PC 4 -PC 7. Control words and status information are also transferred through the data bus buffer. The function of this block is to manage all of the internal and external transfers of both Data and Control or Status words. CS Chip Select. A "low" on this input pin enables the communication between the and the CPU.
RD Read. A "low" on this input pin enables to send the data or status information to the CPU on the data bus. In essence, it allows the CPU to "read from" the WR Write. A "low" on this input pin enables the CPU to write data or control words into the These input signals, in conjunction with the RD and WR inputs, control the selection of one of the three ports or the control word register.
They are normally connected to the least significant bits of the address bus A0 and A1. A "high" on this input initializes the control register to 9Bh and all ports A, B, C are set to the input mode.
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